1. Field of the Invention
The present disclosure relates to a system and a method for generating time bases in low power domain and more particularly relates to a programmable asynchronous divider which can generate divided clock output in any ratio of input clock.
2. Discussion of the Related Art
The current methodologies for time base generation include the well known Asynchronous divider, Synchronous divider and mixture of both.
Asynchronous divider is utilized when the design is aimed at extremely low power applications. In this approach the output of previous Flip-Flop acts as clock to the next stage as shown in FIG. 1.1. Hence dynamic power consumption decreases exponentially down the stage producing a 50% duty cycle clock output. In this case time bases in ratio of powers of 2 (clk/2, clk/4, clk/8 . . . ) with respect to original clock is achievable.
In synchronous divider clock is fed to all the Flip-Flops as shown in FIG. 1.2. The programmability of this divider is such that it leads to divided clock output in any ratio with respect to original clock. The Flip-Flops in the divider can be programmed with any value between 0 and 2n-1 and hence by decoding Q0 through Qn any ratio divided clock can be achieved. However this divider consumes high power and has large gate count.
Synchronous Divider with Asynchronous Prescalar as shown in FIG. 1.3 is often used in low power domain as optimal solution of above two approaches. The asynchronous divider is used as prescalar and programmable synchronous divider is clocked with the output of this prescalar. For an N bit prescalar, divided clock output from synchronous divider will be in multiples of 2N. e.g for 4 bit asynchronous prescalar, synchronous divider can be programmed to get divided clock output of clk/16, 2*clk/16, 3*Clk/16 . . . m*clk/16.